vhdl编的自动售票机 出现it does not hold its value outside the clock edge的错误

Question

问题是 投币 1元和2元 票价2种3元和5元的票
coin1 coin2是投币 finish是完成 money是计钱 change是找钱 get是选择 act是出票
具体代码如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY autosale IS
PORT(
clk: in std_logic;
coin1,coin2:in std_logic;
get3,get5:in std_logic;
finish:in std_logic;
act3,act5:out std_logic;
change:out std_logic;
money:out std_logic_vector(6 downto 0));
end;

architecture rtl of autosale is
signal coin:std_logic_vector(3 downto 0);
signal clk1:std_logic;
begin
com:process(clk1)
begin
if clk1'event and clk1='1' then
change<='0';
if coin1='1'then
if coin<"1001" then
coin<=coin+1;
else coin<="0000";
end if;
elsif coin2='1'then
if coin<"1001" then
coin<=coin+2;
else coin<="0000";
end if;
elsif get3='1'then
if coin>="0011" then
coin<=coin-3;
act3<='1';
end if;
elsif get5='1'then
if coin>="0101"then
coin<=coin-5;
act5<='1';
end if;
end if;
elsif finish='1'then
if coin>"0000"then
change<='1';
coin<=coin-1;
else change<='0';
end if;
end if;
end process com;

code1:process(coin)
begin
case coin is
when"0000"=>money<="0000001";
when"0001"=>money<="0000001";
when"0010"=>money<="0000001";
when"0011"=>money<="0000001";
when"0100"=>money<="0000001";
when"0101"=>money<="0000001";
when"0110"=>money<="0000001";
when"0111"=>money<="0000001";
when"1000"=>money<="0000001";
when"1001"=>money<="0000001";
when others=>money<="1111111";
end case;
end process;

m27:process(clk)
variable q:std_logic_vector(24 downto 0);
begin
if clk'event and clk='1'then
q:=q+1;
end if;
if q="111111111111111111111111"then
clk1<='1';
else
clk1<='0';
end if;
end process m27;
end rtl;
错误都差不多是:Error (10818): Can't infer register for "coin[0]" at autosale.vhd(23) because it does not hold its value outside the clock edge
麻烦高手指教~~~

Answer 1

一个if就要对应一个end if
或者你不想写end if 就要把else 和if连起来写成elsif，这样只要写一个end if就行了。
还有一些其他错误，已改好且编译通过
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY KUOPIN1 IS
PORT(EN,CLK,SIN:IN STD_LOGIC;
SIG_OUT:OUT STD_LOGIC);
END KUOPIN1;
ARCHITECTURE ONE OF KUOPIN1 IS
SIGNAL TEMP:STD_LOGIC_VECTOR(62 DOWNTO 0);
BEGIN
PROCESS(EN,SIN)

CONSTANT PN63:STD_LOGIC_VECTOR(62 DOWNTO 0):="110010010101001101000010001011011111101011100011001110110000011";
CONSTANT PN63_NOT:STD_LOGIC_VECTOR(62 DOWNTO 0):="001101101010110010111101110100100000010100011100110001001111100";
VARIABLE TEMP1:STD_LOGIC_VECTOR(62 DOWNTO 0);
BEGIN

IF EN='1' THEN
TEMP1:=(OTHERS=追问

完全对不上吧