VHDL计数器程序，老是出错，哪位大侠指导一下吧

Question

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sy is
Port ( clk : in std_logic;
reset : in std_logic;
dout : out std_logic_vector(5 downto 0));
end sy;
architecture Behavioral of sy is
signal count: std_logic_vector(5 downto 0);
begin
process(clk,reset,count)
begin
dout<=count;
if reset= '1' then
count <= count+1;
end if;
if count(3 downto 0)="1001" then
count(3 downto 0)<="0000";
count(5 downto 4)<=count(5 downto 4) +1;
else
count(3 downto 0)<=count(3 downto 0)+1;
end if;
if rising_edge(clk) then
if count(3 downto 0)="1001" then
count(3 downto 0)<="0000";
count(5 downto 4)<=count(5 downto 4) +1;
else
count(3 downto 0)<=count(3 downto 0)+1;
end if;
end if;
if count="100011" then
count<="000000";
end if;
end process;
end Behavioral;
老是提示
Error: VHDL error at sy.vhd(25): can't infer register for signal count[5] because signal does not hold its value outside clock edge
Error: VHDL error at sy.vhd(25): can't infer register for signal count[4] because signal does not hold its value outside clock edge
Error: VHDL error at sy.vhd(25): can't infer register for signal count[3] because signal does not hold its value outside clock edge
Error: VHDL error at sy.vhd(25): can't infer register for signal count[2] because signal does not hold its value outside clock edge
Error: VHDL error at sy.vhd(25): can't infer register for signal count[1] because signal does not hold its value outside clock edge
Error: VHDL error at sy.vhd(25): can't infer register for signal count[0] because signal does not hold its value outside clock edge
Error: Can't elaborate user hierarchy
Error: Quartus II Analysis & Synthesis was unsuccessful. 7 errors, 0 warnings
Error: Processing ended: Thu Apr 22 20:30:27 2010
Error: Elapsed time: 00:00:00
Error: Quartus II Full Compilation was unsuccessful. 7 errors, 0 warnings
我实在是无语到了极点啊，迫切需要高手指点，拜托了…………
哦，有一点忘了说，我要实现的是，当reset=1的时候，count自动加一，并且到下边时钟上升沿来的时候再加1，如果高手能帮我再写一个不一样的程序也感谢…………但是输入只能是单脉冲哦 ，我用的是quatusII的编译环境 ，确实挺混乱的，我就是想要达到输入尽量少，同样能实现输出时钟来之前先加1的效果，其实就是调时的效果，还有我觉得这个错误蛮经典的所以想知道解决办法以便以后使用。不行的话也就只好改程序了

Answer 1

你这个程序很奇怪啊，如果是单单的计数器功能就不用搞得那么复杂了，你看是不是题目还有要求别的功能呢？
如果是计数器，我觉得这样会比较简单
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sy is
Port ( clk : in std_logic;
reset : in std_logic;
dout : out std_logic_vector(5 downto 0));
end sy;
architecture Behavioral of sy is
signal count: std_logic_vector(5 downto 0);
begin
process(clk,reset,count)
begin
if reset='0' then 当reset=0时，输出就为0 就复位
count<=(others=>'0');
elsif clk'event and clk='1' then 当时钟上升沿来的时候
count<=count+'1'; 计数加1
if count="111111" then 当加到最大值时，从0开始重新来
count<=(others=>'0');
end if;
end if;
dout<=count;
end process;
end Behavioral;

Answer 2

一个进程里不能有两个时钟驱动！本回答被提问者采纳

Answer 3

我是VHDL语言初学者，斗胆发表一下自己的看法
逻辑有点混乱，看不大懂哦，呵呵
你总是在给count赋值啊
可以把你要实现的逻辑功能说得清楚写么？
我明天下午7点左右上线再看看啊

Answer 4

你用什么编译运行的？我用MAX+plusII运行的，没有错误，但有warnings

Answer 5

都采用边沿触发，试试可不可以?