急急急急!!!!!!!!!!我在用QuartusII做VHDL编程时,发现总是提示同样一个错误,而且很多出都是这样,我怎么改都改不过来,有哪位高手帮我看看啊!!!!!!!!
Error (10001): Verilog HDL or VHDL error at jiaotongdeng.VHD(150): can't infer register for TIME_GREEN2[0] because its behavior depends on the edges of multiple distinct clocks
Error (10001): Verilog HDL or VHDL error at jiaotongdeng.VHD(150): can't infer register for TIME_GREEN2[0] because it does not hold its value outside the clock edge
Error (10001): Verilog HDL or VHDL error at jiaotongdeng.VHD(150): can't infer register for TIME_GREEN2[1] because its behavior depends on the edges of multiple distinct clocks
Error (10001): Verilog HDL or VHDL error at jiaotongdeng.VHD(150): can't infer register for TIME_GREEN2[1] because it does not hold its value outside the clock edge
Error (10001): Verilog HDL or VHDL error at jiaotongdeng.VHD(150): can't infer register for TIME_GREEN2[2] because its behavior depends on the edges of multiple distinct clocks