Error (10818): vhdl 时钟问题

Question

Error (10818): Can't infer register for "a0[0]" at shiftreg.vhd(96) because it does not hold its value outside the clock edge

PROCESS(clk_in,clk_5)
BEGIN
IF clk_5'EVENT AND clk_5='1' THEN
a16<=a15;a15<=a14;
a14<=a13;a13<=a12;
a12<=a11;a11<=a10;
a10<=a9;a9<=a8;
a8<=a7;a7<=a6;
a6<=a5;a5<=a4;
a4<=a3;a3<=a2;
a2<=a1;a1<=a0;
IF clk_in'EVENT AND clk_in='1' THEN
a0<=a;
ELSE
a0<="00";
END IF;
END IF;
错误标在倒数第五行，求高手指导啊

Answer 1

一个进程process只能检测一个信号边沿，所以会有这样的。
你设计的原意大概是这样的吧：时钟上升沿的的时候采样数据，然后在clk_5的上升沿循环读入数据。
有如下两种处理方法
1.用一个process进行处理，不检测clk_5上升沿，直接检测高电平，但是在给clk_5高电平之前要能够保证a的数据已经是想要得到的数据。
PROCESS(clk_in,clk_5)
BEGIN
IF clk_in'EVENT AND clk_in='1' THEN
a0<=a;
ELSE
a0<="00";
END IF;
IF (clk_5='1') THEN
a16<=a15;a15<=a14;
a14<=a13;a13<=a12;
a12<=a11;a11<=a10;
a10<=a9;a9<=a8;
a8<=a7;a7<=a6;
a6<=a5;a5<=a4;
a4<=a3;a3<=a2;
a2<=a1;a1<=a0;
END IF;
END PROCESS;

2.可以分成两个进程process进行处理，一个处理读数据，一个处理数据移位。
PROCESS(clk_in)
BEGIN
IF clk_in'EVENT AND clk_in='1' THEN
a0<=a;
ELSE
a0<="00";
END IF;
END PROCESS;

PROCESS(clk_5)
IF clk_5'EVENT AND clk_5='1' THEN
a16<=a15;a15<=a14;
a14<=a13;a13<=a12;
a12<=a11;a11<=a10;
a10<=a9;a9<=a8;
a8<=a7;a7<=a6;
a6<=a5;a5<=a4;
a4<=a3;a3<=a2;
a2<=a1;a1<=a0;
END IF;
END PROCESS;本回答被提问者和网友采纳