VHDL中一个编译错误： VHDL syntax error at encode.vhd(16) near text "when"; expecting";"代码如下：

Question

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY encode IS
PORT (
a : IN std_logic_vector(7 DOWNTO 0);
c : OUT std_logic_vector(7 DOWNTO 0));
END encode;

ARCHITECTURE arch OF encode IS
SIGNAL c_tmp : std_logic_vector(2 DOWNTO 0);
BEGIN
PROCESS(a)
BEGIN
c_tmp<="111"when a(6)='1' else --此处编译出错
"110"when a(5)='1' else
"101"when a(4)='1' else
"100"when a(3)='1' else
"011"when a(2)='1' else
"010"when a(1)='1' else
"001"when a(0)='1' else
"000";
END PROCESS;

PROCESS(c_tmp)
BEGIN
CASE c_tmp IS
WHEN "000" =>c <= "00000011";
WHEN "001" =>c <= "10011111";
WHEN "010" =>c <= "00100101";
WHEN "011" =>c <= "00001101";
WHEN "100" =>c <= "10011001";
WHEN "101" =>c <= "01001001";
WHEN "110" =>c <= "01000001";
WHEN "111" =>c <= "00011111";
WHEN OTHERS =>NULL;--kongcaozuo
END CASE;
END PROCESS;

END arch;

Answer 1

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY encode IS
PORT (
a : IN std_logic_vector(7 DOWNTO 0);
c : OUT std_logic_vector(7 DOWNTO 0));
END encode;

ARCHITECTURE arch OF encode IS
SIGNAL c_tmp : std_logic_vector(2 DOWNTO 0);
BEGIN
--PROCESS(a)
--BEGIN
c_tmp<="111"when a(6)='1' else --此处编译出错
"110"when a(5)='1' else
"101"when a(4)='1' else
"100"when a(3)='1' else
"011"when a(2)='1' else
"010"when a(1)='1' else
"001"when a(0)='1' else
"000";
--END PROCESS;

PROCESS(c_tmp)
BEGIN
CASE c_tmp IS
WHEN "000" =>c <= "00000011";
WHEN "001" =>c <= "10011111";
WHEN "010" =>c <= "00100101";
WHEN "011" =>c <= "00001101";
WHEN "100" =>c <= "10011001";
WHEN "101" =>c <= "01001001";
WHEN "110" =>c <= "01000001";
WHEN "111" =>c <= "00011111";
WHEN OTHERS =>NULL;--kongcaozuo
END CASE;
END PROCESS;

END arch;

把第一个process注释掉了
process里面是并行语句 不能放在process里面执行

Answer 2

在when前加；
出错行应为
c_tmp<="111"；when a(6)='1' else