vhdl 秒表程序如何用例化语句将各模块连起来

Question

如题所述

Answer 1

给你看个例化的例子：三输入 或门例化2输入或门
library ieee;
use ieee.std_logic_1164.all; ---2输入或门
entity huo is
port(a,b:in std_logic;
c:out std_logic);
end entity;
architecture art of huo is
begin
c<=a or b;
end art;

library ieee;
use ieee.std_logic_1164.all;
entity huo_3 is 3输入或门
port(a,b,c:in std_logic;
d:out std_logic);
end entity;
architecture art of huo_3 is
component huo is --对应将2输入或门的实体写进去，port里面一个字母都不能差
port(a,b:in std_logic;
c:out std_logic);
end component;
signal ab:std_logic;
begin
u1:huo port map(a=>a,b=>b,ab=>c); --对应将两个模块的端口连接起来，
u2:huo port map(ab=>a,c=>b,c=>d);
end art;