Error (10500): VHDL syntax error at mul16b.vhd(19) near text "="; expecting "(", or "'", or "."

Question

程序源
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mul16b is
port( a16,b16:in std_logic_vector(15 downto 0);
dout:out std_logic_vector(31 downto 0));
end mul16b;

architecture count of mul16b is
signal r32 : std_logic_vector(31 downto 0):=(others => '0');
signal s32 : std_logic_vector(31 downto 0):=(others => '0');
signal sign: std_logic_vector(2 downto 0);
begin
sign(2) <= a16(15) xor b16(15);
sign(1) <= a16(15);
sign(0) <= b16(15);
if sign(1) = '1' then
a16 <= not a16 + '1';
end if;
if sign(0) = '1' then
b16 <= not b16 + '1';
end if;
for i in 0 to 15 loop
for j in 0 to 15 loop
r32(i+j) <= a16(i) and b16(j);
end loop;
s32 <= s32 + r32;
r32 <= (others => '0');
end loop;
if sign(2) = '1' then
s32 <= not s32 + '1';
end if;
dout <= s32;
end count;

几处if语句都有错误 大家帮忙改一下 谢谢

Answer 1

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mul16b is
port( a16,b16:buffer std_logic_vector(15 downto 0);
dout:out std_logic_vector(31 downto 0));
end mul16b;

architecture count of mul16b is
signal r32 : std_logic_vector(31 downto 0):=(others => '0');
signal s32 : std_logic_vector(31 downto 0):=(others => '0');
signal sign: std_logic_vector(2 downto 0);
begin
sign(2) <= a16(15) xor b16(15);
sign(1) <= a16(15);
sign(0) <= b16(15);

process(a16,b16)
begin
if sign(1) = '1' then
a16 <= not a16 + '1';
end if;
if sign(0) = '1' then
b16 <= not b16 + '1';
end if;
for i in 0 to 15 loop
for j in 0 to 15 loop
r32(i+j) <= a16(i) and b16(j);
end loop;
s32 <= s32 + r32;
r32 <= (others => '0');
end loop;
if sign(2) = '1' then
s32 <= not s32 + '1';
end if;
end process;

dout <= s32;
end count;